1. Field of the Invention
The present invention generally relates to a semiconductor device, in particular, to a semiconductor device with through-substrate via and the fabrication for the semiconductor device.
2. Description of Related Art
A through-substrate via (TSV), such as a through-silicon via, is a vertical electrical connection passing inter-layer dielectric (ILD) layer and through a silicon wafer or die. TSV technology is an essential structure to form a 3D circuit structure in 3D integrated circuits (IC). It provides interconnection of vertically aligned electronic devices through internal wiring that significantly reduces complexity and overall dimensions of a multi-chip electronic circuit.
A typical TSV process includes formation of TSV holes and deposition of a diffusion barrier layer and a conductive seed layer. A conductive material is then electroplated into TSV holes. Copper is typically used as the conductive material as it supports high current densities experienced at complex integration, such as 3D integrated circuits, and thereby increases device speed.
The conventional method to form the TSV usually needs to polish the deposited Cu to form the conductive seed layer in the TSV hole. However, the liner layer in the TSV hole surrounding the conductive seed layer is also polished with the Cu material. A local uneven structure caused, such as an indent, caused by the polishing process may occur on the top of the liner layer. After the conductive interconnection, such as Cu interconnection, is formed subsequently over the IDL to connect to the TSV, the local indent structure on the top of the liner layer may leave a void, resulting in poor contact to the conductive interconnection.